Fast lock time and low phase noise/spurious are desirable properties in a PLL based synthesizer. However, these are conflicting requirements as fast lock time calls for a wide loop bandwidth whereas low phase noise and spurious calls for a narrow loop bandwidth. A well known approach is to use a wide loop bandwidth initially to lock the loop quickly and then, after the loop has settled, revert to a narrow loop bandwidth for low noise and spurious. Wide loop bandwidth is achieved by increasing the charge pump current by the square of the bandwidth increase, e.g. a 64× charge pump current, Icp, increase for an 8× bandwidth increase. Icp is reduced back to 1× for narrow bandwidth. The 64× increase can be implemented by activating 64 nominally identical charge pump cells or circuits with just one cell or circuit active in narrow bandwidth mode. Prior art fast lock PLLs, based on the dual bandwidth technique suffer from excessively large phase disturbance when the loop bandwidth is reduced. This disturbance is slow to settle out in narrow bandwidth mode, thus the full potential for lock time improvement is not realized. A major contributor to this phase disturbance seems to be the phase step that results with a change in charge pump mismatch when the charge pump current is reduced to 1×. The PLL locks with just enough static phase error to cancel the error due to charge pump up to down mismatch. If the charge pump mismatch in 1× is different from the average mismatch of all elements that are active when the loop has settled in wide bandwidth mode then there will be a corresponding change in the amount of static phase error required to restore the balance when Icp is reduced to 1×.